The present invention relates to the field of integrated circuit (IC) manufacturing. More particularly the present invention relates to system and method of copper plating deposition on an IC wafer.
Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Numerous electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems include processors that have facilitated increased productivity and reduced costs in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. Frequently, electronic systems designed to provide these results include integrated circuits (ICs) on chip wafers with metal components (e.g., copper interconnections between components of the IC). Often these metal components are critical to the functionality of an IC and it is important for them to be manufactured in an efficient and effective manner. Traditional methods of depositing metal in a wafer often include multistep processes that expend significant time performing sequential steps and require extensive resources to be expended focusing attention on relatively delicate operations that are subject to significant defect rates.
The starting material for typical ICs is very high purity silicon. The pure silicon material is grown as a single crystal that takes the shape of a solid cylinder. This crystal is then sawed (like a loaf of bread) to produce wafers typically 10 to 30 cm in diameter and 250 microns thick. Electronic components are then constructed on the wafer by adding multiple layers to the wafer through a process of lithography (e.g., photolithography, X-ray lithography, etc.). Lithographic processes form electronic components in a wafer layer by developing regions with defined electrical characteristics. Complex ICs can often have many different built up layers, with each layer being stacked on top of the previous layer and comprising multiple components with a variety of interconnections.
Most typical photolithographic integrated circuit chip fabrication processes include a deposition phase in which material of differing electrical characteristics is deposited in a space created in a diffusion material. Deposition phases of a lithographic process are often utilized to create components (e.g., resistors, diodes, transistors, etc.) and electrical interconnections between the components. Current technology electrical interconnections often include lines and plugs that are deposited in dielectric layers of the wafer. In the past, lines typically comprised aluminum (or an aluminum alloy) and plugs included tungsten. However, as component sizes become smaller and more layers of metalization are fabricated, interconnections comprising copper are becoming more prevalent. Copper interconnections typically provide several advantages over other materials including lower electrical resistivity and better electromigration resistance.
Usually, a copper damascene process is utilized to deposit copper on a wafer since copper etching is essentially not a viable option. In most damascene processes a deposition material is applied to a substantial portion of wafer surface to be sure that the desired spaces or locations are filled. However, applying the deposition material to most of the wafer surface results in the deposition material effectively creating an unwanted layer that has to be removed in a subsequent step (e.g., removed by a chemical mechanical polishing step). For example, in order to ensure complete filling of a trench, usually excess copper is deposited on most of a wafer surface. However, the excess copper usually interferes with the performance and electrical characteristics of the IC. Excess copper often creates a conductive path past subsequent dielectric material layers designed to provide electrical insulation.
A cross section of a typical conductive line (e.g., copper metalization) produced in the lithographic manufacturing of very large scale integrated (VLSI) device 100 is shown in FIG. 1. After a trench is formed by an lithographic etching process, a thin layer of barrier material 120 (e.g., Ta, TaN, etc.) is deposited to prevent the inter-diffusion between copper and the silicon substrate 130. Then a bulk layer of copper 110 is applied to a substantial area of a wafer surface. The copper deposited between the elevation 150 and elevation 170 is excess copper. Typically, the excess copper is removed in a chemical mechanical process (CMP) to prevent unintentional formation an inappropriate conductive path between devices included in the IC. For example, not removing the excess copper usually results in a layer of conductive material that conducts electricity to inappropriate areas of the integrated circuit (e.g., a short circuit between transistors). After the excess copper and the barrier layer are removed a dielectric layer is applied on top of the wafer surface. Thus, electrically conductive copper paths are confined to trenches forming lines and plugs purposely created between devices.
Removing excess copper also is important to achieving a planarized wafer surface. A level or planarized wafer surface assists lithographic processes to achieve accurate reproduction of very fine surface geometries accurately and integration of more components (resistors, diodes, transistors, and the like) on underlying chip or IC. The primary manner of incorporating more components in a chip is to make each component smaller. Typically, smaller electronic components are built on a chip by increasing optical resolution of a photolithographic process. However, this results in narrowing the depth of focus which is limited by ranges at which a lens remains effective. Depth of focus problems are exacerbated by bumpy topographies on the wafer that usually result during the lithography process of adding layers of material with varying geometric sizes. Thus, in order to focus desirable mask images defining sub-micron geometries onto each of the intermediate photosensitive layers in a manner that achieves the greatest number of components on a single wafer, a precisely flat surface is desired.
Chemical-mechanical polishing (CMP) is the most prevalent method of removing excess conductive copper and obtaining full planarization of a wafer layer. CMP processes usually involve removing excess conductive material by using an abrasive and chemical contact between the wafer and a moving polishing pad covered with a polishing slurry. While typical chemical mechanical polishing processes remove excess copper, they also usually entail detrimental side affects. Copper CMP processes are relatively delicate and require a significant amount of attention. For example, CMP of copper is usually more difficult than tungsten and oxide. Copper is usually prone to both chemical and mechanical attacks. More specifically, copper film typically deposited on a wafer is easily scratched during CMP. As abrasive slurry is consumed during the polishing process the abrasive particles usually scratch the copper.
Utilizing CMP to remove excess copper typically includes time consuming and corrosive multistep operations. Polishing copper by CMP often requires expensive multiple slurries and polishing steps, primarily because the removal rate of copper and barrier layers are significantly different. Most CMP processes are wet processes that require significant time to dry after each CMP step and utilizing xe2x80x9cwetxe2x80x9d fluids significantly adds to the probability of corrosion problems. In addition to difficulties in CMP itself, post-CMP cleaning to remove defects and contaminants from the copper film and surrounding dielectric film is also challenging. Most post CMP cleaning processes include water that is very corrosive to copper lines or plugs. Cleaning chemicals and cleaning tools have to be well designed so that the film is not damaged (e.g., roughened) while it is being cleaned. Post CMP cleaning to remove copper waste from the wafer surface is very critical to device performance since any unremoved waste copper particles have a high probability of diffusing into dielectric materials (e.g., SiO) and interfering with insulation properties. Since copper diffuses into silicon relatively fast, fewer copper CMP steps reduces the exposure of a wafer to potential copper contamination.
What is required is a system and method that facilitates efficient manufacturing of copper interconnections between components of an IC. The system and method should permit copper lines and plugs that are coupled to IC components to be manufactured in a wafer in a manner that maximizes the overall manufacturing wafer output capacity. The system and method should also facilitate efficient removal of excess deposition material and planarization of a wafer layer.
The present invention is a system and method that facilitates efficient material deposition and wafer planarization during IC wafer fabrication. The present invention is particularly useful in facilitating efficient copper deposition and manufacturing of interconnections between components of in IC. A plating deposition polishing system and method of the present invention facilitates deposition of copper interconnection lines and plugs by performing copper deposition and polishing concurrently. The present invention deposition polishing system and method permits copper lines and plugs that are coupled to IC components to be manufactured in a wafer in a manner that maximizes the overall manufacturing wafer output capacity by eliminating sequential delays between copper deposition and wafer planarization. The system and method of the present invention also facilitates efficient planarization of a wafer layer and removal of excess deposition material. In addition, the present invention reduces resources spent on relatively delicate operations and reduces defect rates.
In one embodiment of the present invention, a deposition polishing system comprises a wafer holder, polishing pad component and a CMP plating bath. The CMP plating bath is a container for holding solutions utilized in plating processes (e.g., electroplating, electroless plating, etc.) to deposit metallic material (e.g., copper) on a wafer. A wafer is placed in the plating bath containing plating solution and the polishing pad component impedes the deposition of copper on portions of the wafer surface by applying a frictional force to the surface of the wafer. Copper is deposited in desired locations (e.g., interconnections trenches between components) of a wafer while other areas of the wafer surface are polished. The planarization is controlled to impede copper deposition and remove excess material from portions of a wafer surface while leaving the cooper deposited in other locations (e.g., an interconnection trench). For example, in an electroplating embodiment of present invention, a differential electrical potential is adjusted to ease material removal from the wafer surface. The polishing pad component also facilitates transportation of the plating solution to the wafer and the motion of the polishing pad component agitates the plating solution, enhancing the redistribution of ions in the plating solution to desired deposition locations of a wafer (e.g., an interconnection trench).